TEA1751T_LT_2
?NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 23 December 2009
7 of 29
NXP Semiconductors
TEA1751T; TEA1751LT
GreenChip III SMPS control IC
7.1.2 Supply management
All internal reference voltages are derived from a temperature compensated and trimmed
on-chip band gap circuit. Internal reference currents are derived from a temperature
compensated and trimmed on-chip current reference circuit.
7.1.3 Latch input
Pin LATCH is a general purpose input pin, which can be used to switch off both
converters. The pin sources a current I
O(LATCH)
(80 糀 typical). Switching off both
converters is stopped as soon as the voltage on this pin drops below 1.25 V.
At initial start-up the switching is inhibited until the capacitor on the LATCH pin is charged
above 1.35 V (typical). No internal filtering is done on this pin. An internal zener clamp of
2.9 V (typical) protects this pin from excessive voltages.
Fig 4. Start-up sequence, normal operation and restart sequence
V
CC
LATCH
PROTECTION
PFCSENSE
PFCDRIVER
FBSENSE
FBDRIVER
FBCTRL
VOSENSE
V
O
charging VCC
capacitor
starting
converters
normal
operation
protection
restart
soft start
soft start
I
HV
V
start(VINSENSE)
V
to(FBCTRL)
V
startup
V
th(UVLO)
V
trip
V
EN(LATCH)
V
start(fb)
VINSENSE
014aaa156
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